As the feature sizes of the integrated circuit technology continue to shrink, the electrostatic discharge protection ability of the integrated circuit chips has become a key factor to ensure the reliable operation of the internal circuitry. In an electrostatic discharge phenomenon, transfer of electrostatic charges instantly occurs between two objects with different electric potentials, when such two objects are approaching to each other and/or contacting with each other.
In advanced integrated circuit technology, the gate oxide layer of semiconductor device is very thin. The equivalent capacitance of the gate oxide layer is very small. The electrostatic charge accumulated on the gate oxide layer forms a very large equivalent gate voltage, which will cause device and/or circuit to fail.
The electrostatic shock for integrated circuit chips has different modes, which require different protection circuits. When the electrostatic shock occurs between a power supply pin and a ground pin or between input/output pins, the electrostatic discharge current will flow through the internal functional circuit blocks and cause damages to the internal circuitry. Power supply clamping ESD (electrostatic discharge) protection circuit is an effective remedy against both electrostatic shock modes described above. When a chip is subject to an electrostatic shock, the ESD protection circuit provides an effective shunt circuit to discharge the electrostatic charges and to prevent functional circuits within the chip from any electrostatic shock damages.
FIG. 1 illustrates a conventional ESD protection circuit 1, including a first power supply terminal 10, a second power supply terminal 11, an electrostatic detection unit 12, a logic control unit 13 and a clamping transistor 14. The first power supply terminal 10 connects with the power supply voltage. The second power supply terminal 11 connects with the ground. The electrostatic detection unit 12 includes a resistor 120 and a capacitor 121 connected in series between the first power supply terminal 10 and the second power supply terminal 11. The logic control unit 13 is an inverter.
The ESD protection circuit 1 operates as follows. When an ESD pulse is applied to the first power supply terminal 10, the voltage at the terminal 15 between the resistor 120 and the capacitor 121 is pulled down to the voltage level (ground) of the second power supply terminal 11. After being inverted by the logic control unit 13, the gate voltage of the clamping transistor 14 is pulled up to a high voltage level which turns on the clamping transistor 14 to discharge the electrostatic charge accumulated by the ESD shock. After a time period of the RC time constant for coupling the resistor 120 and the capacitor 121 passes, the voltage at the terminal 15 changes to the voltage level (which is the high voltage level) of the first power supply terminal 10. After being inverted by the logic control unit 13, the gate voltage of the clamping transistor 14 is pulled down to a low voltage level which turns off the clamping transistor 14. The ESD protection operation is then concluded.
When the power on charging voltage is applied to the first power supply terminal 10, the voltage at the terminal 15 remains at the voltage level of the first power supply terminal 10. After being inverted by the logic control unit 13, the gate voltage of the clamping transistor 14 remains at a low voltage level, which ensures the clamping transistor 14 to be turned off in the power on process.
However, the conventional ESD protection circuit has the following limitations. The voltage handling capability of the components in the ESD protection circuit is limited and makes them unable to operate under high voltage condition. The ESD protection circuit has limited voltage handling capability and cannot withstand the high voltage sources of the chip internal circuitry.